基于紧致遗传算法的组合电路测试集压缩

Test set compaction for combinational circuit based on compact genetic algorithm

随着电路集成度和复杂度的不断增加,电路测试所需的测试矢量集的规模也迅速增长。本文针对现有测试集压缩算法全局寻优能力不足的问题,提出一种基于紧致遗传算法的组合电路测试集压缩方法。紧致遗传算法不但具有良好的全局搜索能力,而且其基于小种群进化的特性可以有效地降低计算花费.非常适合处理数据大的大规模测试集压缩问题。对ISCAS-85标准电路测试集的实验表明,与同类方法相比,该压缩方法能够得到更小的测试集。

As the increasing of digital circuit integration level and complexity, the test set size grows rapidly. In this paper, a new test compaction algorithm based on compact genetic algorithm for combinational circuits is presented. Compact genetic algorithm has the ability of global searching, and only needs two individuals for evolution. So compact genetic algorithm can deal with large scale test set compaction and consume less computing resources. The results of experiments on the ISCAS-85 benchmark circuits show that, the proposed method can get smaller test set than other similar methods.