新型流水线ADC的设计与分析

Design and Analysis of a Novel Pipelined ADC

设计和分析了一种新型的流水线式模数转换器。电路设计主要包括一种开关采样差分折叠式共源共栅增益级、两个时钟控制动态比较器组成的两位模数转换器、两位数模转换器。由于采用了电容下极板采样、全差分和开关栅电压自举,有效地消除了开关管的电荷注入效应、时钟馈通效应引起的采样信号的误差,提高了模数转换器的线性度、信噪比、转换精度和速度。该转换器的设计是在0.6μm CMOS工艺下实现,转换器在采样频率为5MHz、信号频率为500kHz时功耗为70mW;SFDR为80 dB。

A novel pipelined ADC is designed. The key circuit design includes a switch sample/hold differential folded common source, common gate op amp, a two-bit ADC,and a two-bit DAC. Since the capacitance bottom plate sampling, the fully differential structure, and the bootstrapped switch are employed, the charge injection error of switch MOSFET and the effect of clock feed-through are eliminated; the linearity, SNR, resolution, and speed of the ADC are improved. The ADC have been simulated in 0.6μm CMOS process with input frequency of 500 kHz, sample frequency of 5 MHz, power consumption of 70 mW, and SFDR of 65dB.