SRAM静态低功耗设计

Technology of Low Power Dissipation for SRAM Designing

在标准的Fabless CMOS工艺线上,由于没有对静态存储器生产进行过专门的工艺优化,在有大规模SRAM嵌入设计的ASIC与SoC电路中,静态电流较大。文章讨论了静态存储器单元静态漏电模式,采用了国内某标准CMOS工艺线提供的0.25μm SPICE模型,使用HSPICE软件对六管静态存储器单元的静态漏电进行了模拟,介绍了一种高可靠、基于0.25μm标准CMOS工艺的低功耗静态存储器设计的解决方案,适用于要求低待机功耗的标准静态存储器、嵌入式静态存储器电路设计。

The/b is always big in the ASIC and SOC circuits embedded with large SRAM, This is because there is no special optimization for the fabrication technology which is used for the SRAM manufactory on normal Fabless CMOS fabrication line. In this article we are mainly discussing the leakage current of the SRAM cell. We simulated the leakage current of 6T RAM cell in the model of 0.25 μ m normal CMOS technology using HSPICE, and developed a highly reliable solution for designing low power dissipation SRAM based on 0.25 μm normal CMOS technology. The new solution is well suited for the design of SRAM and embedded SRAM which demanding low Isb