摘要
采用多路复用流水线的思想,设计基于FPGA仿真测试的RS编解码的改进IBM算法,使用Verilog硬件编程语言实现,进一步提高RS编解码器的运行速度及纠错能力,扩大应用范围。系统设计的时序仿真表明解码器8路复用后的数据率高达116.65 b/s,最大纠错能力为7字节/204字节,达到良好效果。
In order to raise RS codec running speed and the ability of error correcting, expand its application,an improved IBM algorithm of RS codec based on FPGA emulational test is designed.And it adopts pipeline and multiplexing technology. The timing simulatiom of this design indicates that the processing speed of the impoved decoder can reach 116.65bps with a maximum error correcting ratio of 7/204 bytes when the multiplexing number is 8.
出处
《国外电子元器件》
2008年第12期35-36,共2页
International Electronic Elements
