基于级联码的信道编译码设计与FPGA实现

Channel encoder and decoder design and FPGA implementation based on concatenated code

介绍了RS(255,223)码级联卷积(4,3,3)码编译码器的实现,对于编码和译码端不同的结构特点,分别采用并行和串行结构实现。其中RS译码采用欧几里德算法,卷积译码采用维特比算法。同时给出了该编译码器的FPGA实现,按照自上而下的设计流程,在保证速度的同时最大限度地减少了资源占用。

This paper introduces the implementation of RS（255,223） and convolutional（4,3,3） concatenated encoder and decoder. Considering the different characteristics of encoder and decoder, this paper adopts parallel and serial structures respectively. Especially, in the decoder, RS decoding is designed using Euclid algorithm and convolutional decoding is using Viterbi algorithm. FPGA implementations of the encoder and decoder are given. According to top-to-down design flow, the concatenated encoder and decoder in this paper decreases the resource usage furthest at an acceptable speed.