基于FPGA的DDR SDRAM控制器的设计和实现

Design and Implementation of DDR SDRAM Controller Based on FPGA

DDR SDRAM，因其拥有较之SDRAM为两倍的数据读、写速率，已经成为存储器的主流，并得到了广泛的应用，尤其在高速、高精度、高存储深度的数据采集系统中。本文在分析了DDR SDRAM工作原理的基础上，预先在FPGA上利用Verilog硬件描述语言设计实现了DDR SDRAM的读、写以及刷新，给出了DDR SDRAM控制器的状态转换图及结构框图，为进一步与微控制器或数字信号处理器的连接创造条件。目前该控制器已经研制完毕，进一步还可以集成到数据采集系统中。

DDR SDRAM has become the mainstream memory and has been widely used, especially in the data acquisition system with high-speed, high-precision and high-storage depth for its twice data R/W rate than SDRAM. On the basis of analyzing the working principle of DDR SDRAM, the paper introduces a scheme in which Verilog HDL is used to implement reading, writing and refreshing DDR SDRAM in the FPGA, providing the state transition diagram and structure diagram of the DDR SDRAM Controller and preparing for its future links with micro-controller or digital signal processor. The controller has been implemented and can be integrated into the data acquisition system in the future.