基于FPGA的多路抢答器设计

The Design of Multi-channel Responder Based on FPGA

介绍了一种以EDA技术作为开发手段的多路抢答系统的设计和实现。本系统基于VHDL语言,采用FPGA作为控制核心,实现了多路抢答的功能,利用Altera公司的开发平台MAX+PLUSⅡ工具完成了编译、仿真,并下载到FLEX10K系列EPF10K10LC84-4器件进行测试。硬件测试表明系统能够正确显示最先抢答的选手号码,能够对答题时间进行100 s的限时报警以及复位重新抢答。

The design and implementation of Multi-channel responder based on EDA technology is introduced. This system is based on VHDL language, use FPGA as a control core to achieve a multi-channel responder, the Attera＇s development platform MAX ＋ PLUS Ⅱ tool is used for compilation and simulation, the program is downloaded to FLEX10K series EPF10K10LC84-4 chip for testing. The result shows that the system can display the number of the the first player correctly , limit the answer time for 100 seconds of the alarm and reset the responder.