摘要
本文分析和实现了一种基于FPGA的真随机数发生器,采用对延迟链各级输出同时采样的方法来增加输出序列的随机性。电路为纯数字形式,50 MHz 采样时钟采得的输出数据可以无需后处理,直接通过随机性测试,且未发现随机性与采样频率存在显著联系。
An FPGA- based true random number generator （ TRNG ） is proposed. It collects output signals from the delay chain at the same time in order to enhance the randomness of the output sequence. The solution is in a pure digital fashion. Sequences generated at a bit rate of 50 MHz can pass randomness test without being post-processed. Furthermore, variation of the sampling frequency does not affect the randomness of the output sequence
出处
《中国集成电路》
2008年第11期52-55,共4页
China lntegrated Circuit
