期刊文献+

基于随机配置法和输入端缩减技术的统计静态时序分析 被引量:3

Stochastic Collocation Method for Statistical Static Timing Analysis with Input Truncation Technique
下载PDF
导出
摘要 在考虑工艺偏差影响的统计静态时序分析中,针对求解多个随机分布最大值(MAX)的关键问题,提出一种快速MAX算法.该算法将统计输入下的MAX问题转换为求解一组离散配置点上的确定性MAX问题,并用带权最小二乘来计算MAX输出多项式的系数;基于稀疏网格技术有效地减少配置点数,提出输入端缩减技术,进一步提高了MAX的计算效率.ISCAS85基准电路的实验结果表明,该算法较已有的二阶矩匹配算法和基于降维的随机Galerkin算法明显地提高了精度,且效率相当;与10 000次蒙特卡罗的结果相比,中值和方差的相对误差基本小于5%,且有100倍的速度提升. A novel stochastic collocation method with sparse grid and input truncation technique is proposed to perform statistical static timing analysis considering process variations. The proposed method first transforms the key operator MAX with statistical inputs into a set of deterministic MAX problems on a set of collocation points generated with sparse grid, and then solves the unknown coefficients with weighted least square technique. A novel input truncation technique is proposed to further reduce the computational time. Experimental results show that the algorithm achieved obvious improvements on accuracy compared with an existing moment matching based method and a stochastic Galerkin method with dimension reduction technique while kept the same order of efficiency. In comparison with 10 000 Monte Carlo simulation results, the proposed method achieved relative errors of mean and variance mostly below 5%, with nearly 100X speeds up.
出处 《计算机辅助设计与图形学学报》 EI CSCD 北大核心 2008年第12期1527-1534,共8页 Journal of Computer-Aided Design & Computer Graphics
基金 国家自然科学基金重点项目(90307017) 国家自然科学基金(60676018,60806031) 国家“九七三”重点基础研究发展规划项目(2005CB321701) 教育部跨世纪优秀人才培养计划基金 教育部高等学校博士学科点专项科研基金(20050246082) US National Science Foundation grants(CCF-0727791)
关键词 统计静态时序分析 随机配置法 稀疏网格 输入端缩减 工艺参数偏差 statistical static timing analysis truncation process variations stochastic collocation method sparse grid input
  • 相关文献

参考文献19

  • 1Visweswariah C, Ravindran K, Kalafala K, et al. First order incremental block based statistical timing analysis [C]// Proceedings of IEEE/ACM International Conference on Design Automation Conference, San Diego, 2004:331-336.
  • 2Chang H L, Zolotov V, Narayan S, et al. Parameterized block-based statistical timing analysis with non Gaussian parameters, nonlinear delay functions [C]//Proceedings of IEEE/ACM International Conference on Design Automation Conference, Anaheim, 2005: 71-76.
  • 3Zhan Y P, Strojwas A J, Li X, et al. Correlation-aware statistical timing analysis with non-Gaussian delay distributions [C] //Proceedings of IEEE/ACM International Conference on Design Automation Conference, Anaheim, 2005:77-82.
  • 4Zhang L Z, Chen W J, Hu Y H, et al. Correlation- preserved non-Gaussian statistical timing analysis with quadratie timing model [C] //Proceedings of IEEE/ACM International Conference on Design Automation Conference, Anaheim, 2005:83-88.
  • 5Khandelwal V, Srivastava A. A general framework for accurate statistical timing analysis considering correlations [C] //Proceedings of IEEE/ACM International Conference on Design Automation Conference, Anaheim, 2005:89-94.
  • 6Singh J, Sapatnekar S. Statistical timing analysis with correlated non Gaussian parameters using independent component analysis [C] //Proceedings of IEEE/ACM International Conference on Design Automation Conference, San Francisco, 2006:155-160.
  • 7Fang J, Luk W S, Zhao W Q. True worst-case clock skew estimation under process variations using affine arithmetic[J]. Chinese Journal of Electronics, 2007, 16(4) : 631-636.
  • 8Bhardwaj S, Ghanta P, Vrudhula S. A framework for statistical timing analysis using non-linear delay and slew models [C]//Proceedings of the IEEE/ACM International Conference on Computer Aided Design, San Jose, 2006:225-230.
  • 9张富彬,HO Ching-yen,彭思龙.静态时序分析及其在IC设计中的应用[J].电子器件,2006,29(4):1329-1333. 被引量:5
  • 10Satish K Y, Li J, Talarico C, et al. A probabilistic collocation method based statistical gate delay model considering process variations and multiple input switching [C]//Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Messe Munich, 2005:770-775.

二级参考文献13

  • 1Nagal L W.SPICE2:A Computer Program to Simulate Semiconductor Circuits.Memo ERL-M520,Department of Electrical Engineering and Computer Science,University of California,Berkeley,May 1975.
  • 2Hrapcenko V M.Depth and delay in a network[J].Soviet Math Dokl,1978,19(4):1006-1009.
  • 3Kirkpatrick T I,Clark N R.PERT as an Aid to Logic Design[J].IBM Journal of Research and Development,1966,(10):135-141.
  • 4Benkoski J,et al.Timing Verification Using Statically sensitizable paths[J].IEEE Transactions on Computer-Aided Design 1990,9:1073-1084.
  • 5Du D,Yen H,Ghanta S.On the general false path problem in timing analysis[C]//Proceeding of 26th Design Automation Conference,1989:555-560.
  • 6Perremans S,Clacsen L,De Man H.Static Timing Analysis of Dynamically Sensitizable Paths[C]//Proceeding of 26th Design Automation Conference,1989:568-573.
  • 7Roth J P.Diagnosis of Automata Failures:a Calculus and a Method[J].IBM Journal of Research and Develop,July,1966:278-291.
  • 8Start Steven E,Comparini Erik N.Constructing Better Nonlinear Delay Models (NLDM) to Improve Timing Closure[EB/OL].SNUG Boston 2000,http://www.snug-universal.org/cgi-bin/search cgi-Boston,+ 2000.
  • 9De Micheli G,Synthesis and Optimization of Digital Circuits[M].New York:McGraw Hill,1994.
  • 10Visweswariah C,Conn A R.Formulation of Static Circuit Optimization with Reduced Size,Degeneracy and Redundancy by Timing Graph Manipulation[C]//Proceedings of IEEE/ACM International Conference on Computer-Aided Design,1999:244-251.

共引文献4

同被引文献48

  • 1Zou Y, Cai Y C, Zhon Q, et al. Practical implementation of stochastic parameterized model order reduction via Hermite polynomial chaos [C] //Proceedings of IEEE Asia and South Pacific Design Automation Conference, Yokohama, 2007: 367-372.
  • 2Kumar S Y, Li J, Talarico C, et al. A probabilistic collocation method based statistical gate delay model considering process variations and multiple input switching [C]//Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Miinich, 2005:770-775.
  • 3Tao J, Zeng X, Cai W, et al. Stochastic sparse-grid collocation algorithm (SSCA) for periodic steady-state analysis of nonlinear system with process variations [C] // Proceedings of IEEE Asia and South Pacific Design Automation Conference, Yokohama, 2007: 474-479.
  • 4Zhu H L, Zeng X, Cai W, etal. A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology [C] //Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Nice, 2007:1-6.
  • 5Zhang W Y, Yu W J, Wang Z Y, et al. An efficient method for chip level statistical capacitance extraction considering process variations with spatial correlation [C] //Proceedings of the Design, Automation and Test in Europe, Miunich, 2008: 580-585.
  • 6Wang Y, Zeng X, Tao J, et al. Adaptive stochastic collocation method (ASCM) for parameterized statistical timing analysis with quadratic delay model [C] //Proceedings of the 9th International Symposium on Quality Electronic Design, San Jose, 2008; 62-67.
  • 7Patterson T N L. The optimum addition of points to quadrature formulae[J]. Mathematics of Computation, 1969, 22(104) : 847-856+S21-S31.
  • 8Genz A, Keister B D. Fully symmetric interpolatory rules for muhiple integrals over infinite regions with Gaussian weight [J]. Journal of Computational and Applied Mathematics, 1996, 71(2): 299-309.
  • 9Gerstner T, Griebel M. Numerical integration using sparse grids[J]. Numerical Algorithms, 1998, 18:209-232.
  • 10Novak E, Ritter K. High dimensional integration of smooth functions over cubes [J]. Numerisehe Mathematik, 1996, 75: 79-97.

引证文献3

二级引证文献2

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部