集成电路物理设计中的快速可布性评估算法

Fast Routability Estimation for IC Physical Design

集成电路可布性评估在集成电路物理设计中针对布局结果进行有效的评估,作为对布局的反馈信息,并指导后续布线阶段的工作,避免了当后续布线无法完成时再回到前面布局阶段进行重新布局的被动局面,减少了物理设计的迭代周期.提出一种快速可布性评估算法,采用新的基于概率模型的估计算法,利用边界框进行拥挤度的预估,并在概率指导下进行实际布线.文中算法可以在很短的运行时间内对拥挤情况进行较为准确、客观的分析,线长较短.

Routability estimation plays an important role in IC physical design. With the fast feedback on congestion, the estimator serves incremental placement and guides routing to shorten the physical design time. A routability analysis algorithm for IC physical design is proposed. This estimation algorithm firstly extends an existing combinatorial model with the extended bounding box for flat two-pin nets/sections to pre-estimate congestion probabilistically. Then, it routes all nets guided by the pre-estimation to get more exact congestion estimation, which is fast since it does not include any iteration/optimization as a router does. The idea is net-order-independent. This algorithm can obtain a uniform usage of routing resources by probability.