基于电路拓扑结构分析的等价性验证方法

Combinational Equivalence Checking Based on Circuit Topology Analysis

随着集成电路设计规模的日益增大,结合多种推理引擎已成为组合电路形式化等价性验证的重要手段.提出一种基于电路拓扑结构分析的组合等价性验证方法,将电路的拓扑结构与验证算法的复杂性关联起来.在验证过程开始之前,利用min-cut方法计算表征电路复杂性的"电路宽度",以确定最佳的推理引擎,避免了传统的引擎切换过程,提高了算法的效率.针对ISCAS 85电路的实验结果表明了该方法的效率和可行性.

With the increasing of VLSI circuit size, using multiple verification engines has been an important methodology of formal equivalence checking for combinational circuits. A combinational equivalence checking method based on circuit topology analysis is presented. This method can correlate the circuit topology to the complexity of verification algorithm, thus decide the optimal verification engine beforehand and improve the efficiency of equivalence checking. The experimental results on ISCAS＇85 benchmark circuits show the efficiency and the feasibility of the proposed method.