指令cache体系结构级功耗控制策略研究

The Research on Power Controlling Policies for Instruction Cache with Architecture Level Methods

随着工艺尺寸缩小及处理器频率提高,功耗问题已成为当代微处理器设计面临的主要挑战.传统的指令cache(I-Cache)功耗控制策略一般只单独降低指令cache的动态或者静态功耗.提出的两种改进的功耗控制策略,基于昏睡指令cache体系结构,能够更有效地同时降低指令cache的动态和静态功耗.一种称作"使用双预测端口路预测器的多路路预测策略",另一种称作"基于分阶段访问cache的按需唤醒预测策略",分别用于处理器前端流水线级数保持不变和可以增加额外前端流水线级数两种情形.实验结果表明:与传统的策略相比,提出的两种策略具有更优的能量效率,可以在不显著影响处理器性能的前提下,更有效地降低指令cache和处理器的功耗.

As feature size shrinks and the frequency increases,power dissipation has become the main restriction on micro- processor design. The traditional power controlling policies for instruction cache （I-Cache） are used for reducing the dynamic access power or the leakage power respectively. Two improved power controlling policy are proposed to reduce the dynamic and leakage power at the same time more efficiently. One is called ＂Multi-Way Way Prediction （MWWP） policy with a Two Prediction-ports Way Predictor （TPWP）＂ that is proposed for the case of keeping the original level of the front-end pipeline stages. The other is called ＂Phased cache with On-demand Wakeup Prediction, （POWP） policy＂ that is proposed for the case of allowing new stage is inserted into original front-end pipeline. The research results show that： compared with traditional power controlling policies, proposed policies have the better power efficiency. They can reduce the power of whole processor more efficiently with less performance degradation.