多核SoC可扩展性设计技术研究

Research on Extensibility of Hierarchy Bus Based FPGA prototype for Multi-Processor System-on-Chip

近年来,使用多核SoC代替传统的单处理器系统,在提高系统并行性方面显示出了巨大的优势。本文在已有层次化总线结构MPSoC的基础上,研究多核SoC原型芯片可扩展性设计问题。在RTL级设计了上述平台,并用FPGA进行原型验证,以流水矩阵乘法为例研究其在不同工作负载下的加速比变化。实验结果表明,在6个处理器的情形下,循环次数为6次时加速比仅为4.10;随着循环次数增多,加速比可达5.48。研究表明多核层次化总线原型芯片的性能提升百分比以及面积增加百分比与处理器数目成正比。可以通过增加处理器的数目来提升MPSoC原型芯片的性能。

In recent years, multi-processor system on chip （MPSoC） has become one of the mainstream design technologies in IC design field. Based on an existing in-house designed MPSoC, this paper focuses on the extensibility study of the hierarchy bus based MPSoC FPGA prototype. The MPSoC platform was implemented at RTL level, and on-chip communication architecture was extended from 4-cores to 6-cores. The extended MPSoC was implemented and verified on Altera FPGA. Qualitative experiments were carried out using pipelined-matrix-multiplication programs. The multiplication time was parameterized to generate different workloads. The experiment results show that under the condition of 6 processors, when the number of multiplication cycles is 6, the speedup is only 4. 10, as the workload increases the speedup comes up to 5.48. Area overhead was also analyzed, the result shows that the performance enhancement is achieved at the cost of high area overhead that is an increment of 52. 9%, and there is a performance decrease trend in terms of unit speedup in the hierarchy bus based MPSoC.