基于ARM9的AC＇97控制器的电路的改进

The Improvement of AC＇97 Controller Based on the ARM9

针对基于ARM9框架下AC＇97控制器在录放音时有噪音的不足以及在FPGA验证下频繁出现异常重启的缺点，该文对该控制器的异步FIFO进行改进——重新设计FIFO状态判断标志以正确地配合DMA对其进行读写的时序。在对其进行Verilog硬件代码的修改后．在Altera公司的StratixⅡ系列FPGA上进行功能验证。

In allusion of the defect that the AC＇97 controller will make noses as recording and playing under ARM9 Frame, as well unconventionally restart when FPGA Validating. This text improves the Controller＇s asynchronous FIFO for FIFO state judgment system in order to work with DMA reading or writing in certain sequence. And also can function validating on Altera＇s Stratix series Ⅱ - FPGA, after revise FIFO on Verilog code.