USB2.0设备控制器IP核的设计与验证

Design and Verification of USB2.0 Device Controller IP Core

文中设计了一种符合USB2.0规范并具有AHB接口的USB设备控制器IP核。首先根据功能将设备控制器划分成多个独立的子模块,并详细介绍了各个子模块的结构和设计方法;最后使用VerilogHDL硬件描述语言完成RTL代码,为所设计的IP核建立了仿真环境和FPGA硬件验证环境。该设备控制器能够完成全速和高速传输模式以及4种传输方式:控制传输、批量传输、中断传输、同步传输,并且支持挂起和远程唤醒的功能,这些功能在FPGA上得到了验证,可适用于各种USB设备类的开发。

This paper presents the design and implementation of a USB device controller that meets the USB2.0 specification with AHB interface. The whole system is divided into several independent modules according to the system functions with the functions and design methodology for each of the child modules introduced. Finally after the RTL coding is completed using Verilog HDL, a simulation environment and FPGA hardware verification environment for this IP core are constructed. This device controller supports full speed mode and high speed mode. Additionally, it supports four types of transfer ： control transfer, bulk transfer, interrupt transfer and isochronous transfer. Suspend and remote wakeup modes are also supported. All these functions are verified on FPGA so that this IP core is useful for the development of all kinds of USB devices.