摘要
This paper implements the study on the Dose Rate Upset effect of PDSOI SRAM （Partially Depleted Silicon- On-Insulator Static Random Access Memory） with the Qiangguang-I accelerator in Northwest Institute of Nuclear Technology. The SRAM （Static Random Access Memory） chips are developed by the Institute of Microelectronics of Chinese Academy of Sciences. It uses the full address test mode to determine the upset mechanisms. A specified address test is taken in the same time. The test results indicate that the upset threshold of the PDSOI SRAM is about l×10s Gy（Si）/s. However, there are a few bits upset when the dose rate reaches up to 1.58 x 109 Gy（Si）/s. The SRAM circuit can still work after the high level 3~ ray pulse. Finally, the upset mechanism is determined to be the rail span collapse by comparing the critical charge with the collected charge after γ ray pulse. The physical locations of upset cells are plotted in the layout of the SRAM to investigate the layout defect. Then, some layout optimizations are made to improve the dose rate hardened performance of the PDSOI SRAM.
This paper implements the study on the Dose Rate Upset effect of PDSOI SRAM （Partially Depleted Silicon- On-Insulator Static Random Access Memory） with the Qiangguang-I accelerator in Northwest Institute of Nuclear Technology. The SRAM （Static Random Access Memory） chips are developed by the Institute of Microelectronics of Chinese Academy of Sciences. It uses the full address test mode to determine the upset mechanisms. A specified address test is taken in the same time. The test results indicate that the upset threshold of the PDSOI SRAM is about l×10s Gy（Si）/s. However, there are a few bits upset when the dose rate reaches up to 1.58 x 109 Gy（Si）/s. The SRAM circuit can still work after the high level 3~ ray pulse. Finally, the upset mechanism is determined to be the rail span collapse by comparing the critical charge with the collected charge after γ ray pulse. The physical locations of upset cells are plotted in the layout of the SRAM to investigate the layout defect. Then, some layout optimizations are made to improve the dose rate hardened performance of the PDSOI SRAM.
