期刊文献+

声码器中一种四级可重构ALU的研究与设计

Research and Design of a Four-stage Reconfigurable ALU in Vocoder
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摘要 在面向语音编解码算法实现的高性能声码器设计中,支持可变长VLIW指令集的ALU单元是实现其设计目标的重要环节.本文提出一种四级可重构的ALU设计,以前缀算法加法器为核心,并通过操作数和资源的重构,能在单周期内完成81种复合算术逻辑运算,同时将其控制编码压缩了58.93%以适应指令集的宽度约束,高效实现了算法中潜在的高并行性,很好的满足了运算密集型的算法应用需求. In the design of high performance vocoder based on speech compressing algorithms,the ALU module is essential for its design goal. This paper proposes the design techniques of a four-stage reconfigurable ALU based on the 8-bit adders using prefix algorithm. The ALU can manipulate 81 kinds of compound arithmetic and logic operations in a single cycle via operands and resources reconfiguration, and by using coding compression, its control codes can be reduced by 58.93%, which meets the variable length VLIW instruction-set's restriction. According to the simulation results, the proposed ALU meets the need of arithmetic intensive applications and implements the parallelism in the algorithms effectively.
作者 荆涛 王沁
出处 《小型微型计算机系统》 CSCD 北大核心 2008年第12期2277-2280,共4页 Journal of Chinese Computer Systems
基金 国家自然科学基金项目(60572081)资助
关键词 声码器 算术逻辑运算单元 可重构 并行性 voeoder ALU reconfigurable parallelism
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参考文献6

  • 1Zhang Jian-wei,He Tian-hOng, Li Jun-lin,et al. 0.6kb/s high quality speech coding algorithm[J].Journal of Tsinghua University, 2003, 43(4):449-452.
  • 2Manoj K J,Balakrishnan M, Kumar A. ASIP design methodologies:survey and issues[C]. Proc. 14th Int'l Conf. VLSI Design, Los Alamitos, CA: IEEE Computer Society Press, 2001, 76-81.
  • 3Fan Chang-yong. 32-bit RISC microprocessor module design [D]. Beijing University of Technology, 2003.
  • 4段然,樊晓桠,高德远,沈戈.可重构计算技术及其发展趋势[J].计算机应用研究,2004,21(8):14-17. 被引量:19
  • 5Brent R P,Kung H T. A regular layout for parallel adders[J]. IEEE Trans. Comput. , 1982,32(3) :260-264.
  • 6俞磊,罗金平,周兴铭.VLIW技术的最新发展[J].计算机工程,2002,28(1):1-3. 被引量:2

二级参考文献27

  • 1G Estrin,et al. Parallel Processing in a Restructurable Computer System [ J ]. IEEE Trans. Electronic Computers, 1963, ( 12 ): 747 - 755.
  • 2H Singh, M Lee, G Lu, et al. MorphoSys: An Integrated Re-configurable Architecture[ C]. Proc. NATO Symp. System Concepts and Integration, Monterey, CA, 1998.
  • 3Hartenstein R. Trends in Reconfigurable Logic and Reconfigurable Computing [ C ]. Electronics, Circuits and Systems, 9th International Conference on,2002. 801 - 808.
  • 4H Sing, h, Ming-Hau Lee, et al. MorphoSys: An Integrated Reconfigurable System for Data-parallel and Computation-intensive Applicatons [ J ]. Computers, IEEE Transactions on,2000,49 ( 5 ) :465-481.
  • 5Xilinx Corporaton[ EB/OL]. http ://www. xilinx. com,2002-12.
  • 6Hauser J R,Wawrzynek J. Garp:A MIPS Processor with a Reconfigurable Coprocessor. FPGAs for Custom Computing Machines, Procee dings[ C]. The 5th Annual IEEE Symposium on, 1997.12-21.
  • 7PACT Corporation[ EB/OL]. http://www. pactcorp. com,2003-05.
  • 8Greenbaum J. Reconfigurable Logic in SoC Systems[ C ]. Custom Integrated Circuits Conference, Proceedings of the IEEE ,2002.5-8.
  • 9A Dehon. Reconfigurable Architecture for General Purpose Computing [ R]. Report no. AITR 1586,MIT AI Lab. ,1996.
  • 10Becker F. Configurable Systems-on-chip: Commercial and Academic Approaches. Electronics, Circuits and Systems [ C ]. 9th International Conference,2002. 809 - 812.

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