低带宽全搜索VBSME结构的优化设计

Optimized Design of Low-bandwidth Full Search VBSME Architecture

为支持H.264/AVC可变块运动估计(VBSME)要求,提出一个高性能的二维脉动阵列结构,该结构具有数据重传次数少,存储器带宽要求低的特性.对结构中存在大量延迟寄存器开销的问题,用基于数据流的AON网络模型对阵列结构的计算依赖关系进行分析,并使用动态规划算法,得到了优化的结构设计.

A high-performance 2-D systolic VLSI architecture, featuring low redundancy memory access count （RAC） as well as low memory bandwidth requirement,has been proposed to support variable block size motion estimation （VBSME） required in H. 264/AVC standard. Given the delay registers overhead in the structure, AON network model based on data flow is employed to analyze the computational dependency of the array structure. Then dynamic programming algorithm is applied to achieve a structurally optimized VBSME design.