基于VHDL语言的数字频率计的设计与仿真

Design and Simulation of Digital Cymometer based on VHDL

介绍了一种采用VHDL语言设计数字频率计的方法,利用测周法和测频法相结合的原理,对传统的频率计进行了改进,实现了0 Hz^1 MHz的频率测量范围,并且给出了仿真结果.仿真结果表明,该频率计具有体积小、测量精度高、可靠性好等特点,同时可以通过修改程序达到扩大测量范围的目的.

This paper introduces a digital eymometer methods on VHDL using the principle of eyhele measurement and frequency meas- urement, making the improvement to the traditional eymometer, achieving a 0 - 1 MHZ frequency range and giving the simulation results. The simulation results show that the cymometer is small in size, high accuracy, reliability and other charaeter isties; it can modify the program to expand the range of purposes as well.