无线传感器网络节点芯片的软/硬件协同低功耗设计技术

Implementation of Low-Power S/H Co-Design for WSN Node SOC

文章在深入研究了传感器节点芯片软硬件体系架构后,分析了CMOS工艺下集成电路的功耗来源和设计传感器节点芯片的功耗要求,研究了三种降低功耗的硬件电路设计方法,并推导了相应的公式:电源调节模块改进了传统的LDO电路结构,实现了双环路动态补偿方法,对芯片内部电路进行多等级电源供电;把芯片电路划分为四个工作状态,在不同的工作状态,各电路模块按照不同的活动级别被激活或者被关断耗;对影响功耗很大的时钟网络进行优化,采用多级时钟网络并根据不同电路模块选择不同的时钟频率。这些研究,将对后续的传感器节点芯片设计工作,具有重要的意义。

Based on the research of the software and hardware design architecture for WSN node SOC, this paper analyzes the power dissipation of CMOS digital circuit and the power requirement of the WSN node chip, three power optimization methods for circuits are implemented. Improve the traditional LDO structure by realizing dual-loop dynamic compensation for the on-chip voltage regulator, to supply different grades voltage for different circuits. Four flexible power modes are implemented for reducing unnecessary power consumption according to dynamic power management. And multilevel clock networks and different clock frequency are used by the actual need of circuits. In the end, a range of power optimization methods for software design are introduced.