多芯片组件(MCM)的互连延时

Interconnection Delay in High-speed Multi Chip Modules

高速、高性能MCM中，往往把电路设计在欠阻尼小振荡输出的工作状态，以保持信号在互连传输线中的快速和平稳传播。已有文献关于互连延时的研究往往是针对过阻尼或欠阻尼大振荡工作状态，即对应于通常的IC和PCB互连，即使对高速VLSI互连延时的研究，考虑到计算的复杂性和有效性，也往往只处理过阻尼和欠阻尼大振荡两种状态，因此若将给出的结果用于研究MCM互连延时，误差相当大甚至无效。本文提出了一种研究MCM互连延时的方法，并给出了延时在3种工作状态下与各物理参数之间的确定公式。

In high-speed, high-performance design of a Multi Chip Module (MCM), it is often to reach an underdamped state in a small oscillation to result in fast and stable signal propagation. Many papers have been published on the study of interconnection delay. In most cases, however, the interconnection delay has been analyzed by using overdamped state or underdamped state in a large oscillation output. It corresponds to interconnection levels: on a Printed Circuit Board (PCB), large scale integrated circuit. And the interconnection delay has also been analyzed in the same way for high-speed LSI because of a resonable compromise between accuracy and speed. If using this way to study interconnection delay in MCM, there would be large error or inefficient. This paper presents a formal analysis of the interconnection delay in MCM circuits. Depending upon the circuit parameters, three delay formulas are respectively deliver for the three delay domains.