一类有限域乘法器的设计实现

Implementation of Bit-Parallel Multiplier over Finite Field

提出了一种基于有限域内移位三项式基及其弱共轭基的比特并行乘法器的新结构。在由三项式生成的域内,此种结构的比特并行乘法器易于设计者使用硬件描述语言实现。采用Encounter软件对该结构进行布局布线后,发现其面积与关键路径时延都达到了设计目标的要求,在设计性能和硬件约束条件上取得了比较好的平衡。

New structures of bit-parallel multiplier based on shifted polynomial basis （SPB） and its weakly dual ba- sis（WDB） over finite field are proposed. To the fields generated by trinomials, the structure of the proposed bit-par- allel multiplier is easy for a designer to implement the proposed multipliers into hardware for their regular struc- tures. Placement ~ Wire Routing using Encounter indicate that the proposal is thoroughly tested and proved to be good,and it balances the capability requirement and hardware consumption.