VITAL——设计ASIC模型的VHDL基准

VITAL——A VHDL INITIATE FOR ASIC MODEL DESIGN

ＶＩＴＡＬ是ＩＥＥＥ新近制定的一个用ＶＨＤＬ建立ＡＳＩＣ模型库的基准，它为ＡＳＩＣ库的建立、电路设计的描述提供了便利的、格式相对固定的描述方法，并为提高模拟性能提供了依据和基础．本文介绍ＶＩＴＡＬ的基本内容，并介绍用ＶＩＴＡＬ描述电路模型的方法．

\ VITAL (VHDL Initiate Towards ASIC Library) is a new IEEE standard of VHDL initiate for building ASIC models. It supports a description specification and standard packages: Timing Package and Primitive Package, for designer to build the ASIC model, to design a circuit conveniently and formally. This paper introduces the basic contents and the approach to describe circuit models by using VITAL.