ESD保护器件在多晶硅上的实现

ESD protection devices on polycrystalline silicon

静电放电现象是导致集成电路损坏的一个重要原因,目前绝大多数集成电路中的ESD保护电路都是在硅片上实现的,这将占用一定的硅片面积,提升电路的成本。如果能够在多晶硅层(垂直空间)实现ESD保护器件,就能够节约一定的面积,从而节约成本。介绍了对于在多晶硅上实现的静电保护器件的研究结果。

Electrostatic discharge phenomenon is the principal cause of the integrated circuits＇ damage. At present most of the ESD protection circuits are based on the silicon layer, this will occupy the surface and augment the costs of the circuits. If the ESD protection devices can be produced on the polycrystalline silicon layer （vertical）, this will save the surface on silicon and reduce the costs. This paper presents the research results about ESD protection devices on polycrystalline silicon.