多应力结构CMOS器件的模拟研究

Simulation Research on CMOS Device with Multiple Stressors

使用TCAD仿真工具Sentaurus在45 nm节点工艺下模拟研究了包含多应力结构的应变Si CMOS器件。模拟所得的开关电流比与相同节点工艺下报道的实验结果能很好吻合,验证了所用模型及方法的正确性。用Sentaurus工艺模拟工具得到了器件内部的应力和掺杂分布,并用Sentaurus器件模拟工具分析了各种应力结构对电学特性的影响。结果表明:在nMOS中,SMT和DSL能有效提高器件性能,而STI却会降低器件性能;在pMOS中,SiGe S/D和DSL的存在是性能改善的主要原因,而STI对性能改善的帮助较小。

CMOS device with multiple stressors was studied using the TCAD simulation tool Sentaurus at 45 nm process node. The on/off current ratio obtained by simulation shows the same tendency as published experiment results, verifying the correctness of the simulation model and method used. The stress and doping distributions in the device were obtained by Sentaurus process, and the effects of various stressors on the electrical properties were investigated by Sentaurus device. Results indicate that stresses induced by SMT and DSL can improve the electrical properties of the strained nMOS effectively, while STI degrades the device performance. On the other hand, stresses induced by SiGe S/D and DSL can improve the performance of pMOS significantly, and the stress caused by STI shows smaller effect on the performance enhancement.