用于高速ADC的低抖动时钟稳定电路

Low Jitter Clock Stabilizer for High-Speed ADC

介绍了一种用于高速ADC的低抖动时钟稳定电路。这个电路由延迟锁相环(DLL)来实现。这个DLL有两个功能:一是通过把一个时钟沿固定精确延迟半个周期,再与另一个沿组成一个新的时钟来调节时钟占空比到50%左右;二是调节时钟抖动。该电路采用0.35μm CMOS工艺,在Cadence Spectre环境下进行仿真验证,对一个8 bit、250 Msps采样率的ADC,常温下得到的时钟抖动小于0.25 ps rms(典型的均方根)。

A low jitter clock stabilizer of a high-speed ADC was described. The circuit was realized by delay-locked loop （DLL）. The DLL has two functions： firstly, it can adjust the clock duty cycle to about 50% by delaying the clock edge exactly and stably at half a period, then with another clock edge, a new clock is formed ; secondly, it can adjust the time jitter. The circuit was fabricated in a 0. 35μm COMS process, and it is simulated in the environment of Cadence Spectre. For an ADC whose sampling rate is 250 Msps, the time jitter is lower than 0.25 ps rms （typical root mean square）.