期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

Evolution of MPP SoC architecture techniques 被引量：7

Evolution of MPP SoC architecture techniques
原文传递
导出
摘要 The evolution of chip architecture is discussed in this paper. Then MPP SoC architectures according to three kinds of computing paradigms are analyzed. Based on these discussions and analyses, array processor architecture for unified change is presented, which could implement the simplification, effectiveness and versatility of both data level and non-data level parallel algorithm＇s programming. The evolution of chip architecture is discussed in this paper. Then MPP SoC architectures according to three kinds of computing paradigms are analyzed. Based on these discussions and analyses, array processor architecture for unified change is presented, which could implement the simplification, effectiveness and versatility of both data level and non-data level parallel algorithm＇s programming.
作者 SHEN XuBang
机构地区 Xi'an Microelectronics Research Institute
出处 《Science in China(Series F)》 2008年第6期756-764,共9页 中国科学（F辑英文版）
关键词 MPP SOC array processor ARCHITECTURE MPP, SoC, array processor, architecture
分类号 TP3 [自动化与计算机技术—计算机科学与技术]
  • 相关文献

参考文献11

  • 1沈绪榜,张发存,冯国臣,车得亮,王光.计算机体系结构的分类模型[J].计算机学报,2005,28(11):1759-1766. 被引量：10
  • 2Manners D,Makimoto T.Living with the Chip[]..1995
  • 3Le H Q,Starke W J,Fields J S, et al.IBM POWER6 microarchitecture[].J Res Dev.2007
  • 4AMD Corp.AMD Opteron?[].Product Data Sheet.2004
  • 5Ratner M,Ratner D, et al.Nanotechnology——A Gentle Introduction to the Next Big Idea[]..2003
  • 6Macias N I.Adaptive method for growing electronic circuits on an imperfect synthetic matrix[].Biosystems Engineering.2004
  • 7Adleman L M.Computing with DNA[].Scientific American.1998
  • 8Flynn M J.Very high speed computing systems[].Proceedings of the IEEE.1966
  • 9NVIDIA Corp.NVIDIA GeForce 8800 Architecture Technical Brief[]..2006
  • 10Persson E.ATI Radeon? HD 2000 programming guide[].AMD Graphics Products Report.2007

二级参考文献10

  • 1Manners D., Makimoto T.. Living with the Chip. London: Chapman & Hall, 1995
  • 2Hartenstein R.. Data-stream-based computing: Models and aarchitectural resources. Kaiserslautern University of Technology, Germany. http://hartenstein.de
  • 3Trelearen P.C. et al.. Data-driven and demand-driven computer architecture. ACM Computing Surveys, 1982, 14(1): 93～143
  • 4Jantsch A., Tenhunen H.. Networks on Chip. Boston: Kluwer Academic Publishers, 2003
  • 5Flynn M.J.. Very high speed computing systems. Proceedings of the IEEE, 1966, 54: 1901～1909
  • 6Dasgupta S.. Computer Architecture-A Modern Synthesis. New York: John Wiley & Sons, 1989
  • 7Heysters P.M., Smit J., Smit G.J.M., Havinga P.J.M.. Exploring energy-efficient reconfigurable architectures for DSP algorithms. In: Proceedings of the PROGRESS 2000 Workshop, 2000, 37～46
  • 8Enzler R.. Architectural trade-offs in dynamically reconfigurable processors. Swiss Federal Institute of Technology (ETH), Zurich: Technology Report 15423, 2004. http://www.ife.ee.ethz.ch /～enzler/pub/phdthesis04.html
  • 9Deprettere F. eds.. Embedded Processor Design Challenges. Berlin Heidelberg: Springer-Verlag, 2002
  • 10Kung H.T.. Why systolic architecture? Computer, 1987, 15:37-46.

共引文献9

同被引文献28

  • 1沈绪榜.星载嵌入式计算机的技术展望[J].电子产品世界,2008,15(1). 被引量：1
  • 2许社教.三维图形系统中两种坐标系之间的坐标变换[J].西安电子科技大学学报,1996,23(3):429-432. 被引量：22
  • 3沈绪榜.航天时代的嵌入式图像处理技术[J].电子产品世界,2007,14(1):40-40. 被引量：2
  • 4Licciardo G D,Albanese L F.Design of a Context-adaptive Variable Length Encoder for Real-time Video Compression on Reconfigurable Platforms[J].IET Image Processing,2012,6(4):301-308.
  • 5Dixit H V,Jeyakumar A,Kasat P S,et al.VLSI Design of Fast DCTQ-IQIDCT Processor for Real Time Image Compression[C]//Proceedings of Tenth International Conference on Wireless and Optical Communications Networks.Piscataway:IEEE,2013:1-5.
  • 6Orchard G,Zhang J,Suo Y,et al.Real Time Compressive Sensing Video Reconstruction in Hardware[J].IEEE Journal on Emerging and Selected Topics in Circuits and Systems,2012,2(3):604-615.
  • 7Coates A,Baumstarck P,Le Q,et al.Scalable Learning for Object Detection with GPU Hardware[C]//Proceedings of IEEE/RSJ International Conference on Intelligent Robots and Systems.Piscataway:IEEE,2009:4287-4293.
  • 8Vangal S,Howard J,Ruhl G,et al.An 80-tile 1.28 TFLOPS Network-on-chip in 65nm CMOS[C]//Proceedings of IEEE International Solid-State Circuits Conference.Piscataway:IEEE,2007:98-589.
  • 9Hutchings B,Nelson B,West S,et al.Comparing Fine-grained Performance on the Ambric MPPA Against an FPGA[C]//Proceedings of International Conference on Field Programmable Logic and Applications.Piscataway:IEEE,2009:174-179.
  • 10Zhang Y,Yan C,Dai F,et al.Efficient Parallel Framework for H.264/AVC Deblocking Filter on Many-core Platform[J].IEEE Transactions on Multimedia,2012,14(3):510-524.

引证文献7

二级引证文献50

Science in China(Series F)
2008年 第6期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部