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片上网络技术发展现状及趋势浅析 被引量：11

The State-of-the-art and perspectives on Network-on-Chip
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摘要 半导体制造工艺的快速发展使得片上可以集成更大规模的硬件资源,片上网络的研究试图解决芯片中全局通信问题,使得从基于计算的设计转变为基于通信的设计,并实现可扩展的通信架构。本文回顾和总结了现有NoC研完工作,指出NoC是当前片上通信发展的主流趋势,并分析了当前NoC关键技术瓶颈,最后预测了多核的技术和产业发展趋势。
作者 李丽 许居衍
机构地区 南京大学物理系微电子设计研究所 中电集团第五十八研究所
出处 《电子产品世界》 2009年第1期32-37,共6页 Electronic Engineering & Product World
关键词 片上网络(NoC) 存储结构 并行软件 功耗管理
分类号 TN47 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献9

  • 1Benini L De Micheli G. Networks on chips: a new SoC paradigm[J]. IEEE Computer, Volume 35, pp. 70--78, January 2002
  • 2Jantsch A, Tenhunen H. Networks on Chip[M]. Kluwer Academic Publishers, 2003
  • 3Millberg M,Nilsson E, Thid R,Kumar S,Jantsch A.The Nostrum backbone-a communication protocol stack for networks on chip[R]. Proceedings of the VLSI Design Conference, January 2004
  • 4Ogras U, Hu J, Marculescu R.Key Research Problems in NoC Design: A Holistic Perspective[J] Proc. Hardware-Software Co- Design and System Synthesis, (CODES+ISSS), September, 2005
  • 5Pasricha S, Dutt N D. A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC[C]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 26,?issue 3,March 2007 Page(s):408 C 420
  • 6Kandemir M, Dutt N. Memory Systems and Compiler Support for MPSoC Architectures[J], Multiprocessor Systems-on- Chips, 2005P 251-281
  • 7张云泉.多核时代对软件设计的挑战.计算机世界报,2007,(23).
  • 8张戈,张量,杨荣秋.纳米级工艺下多处理器功耗评估与优化技术[J].中国集成电路,2008,17(7):25-31. 被引量：2
  • 9Liu C, Chen J H, Manohar R, Tiwari S. Mapping system-on-chip designs from 2-D to 3-D ICs[C]. IEEE International Symposium on Circuits and Systems, 2005. ISCAS 2005, 23-26 May 2005 Page(s):2939 - 2942 Vol. 3

二级参考文献19

  • 1[1]D.Brooks,V.Tiwari,and M.Martonosi.Wattch:A framework for architectural-level power analysis and optimizations,In Proceedings of the 27th Annual International Symposium on Computer Architecture,pp.83-94,June 2000
  • 2[2]W.Ye,N.Vijaykrishnan,M.Kandemir and M.Irwin.The design and use of simplepower:a cycle-accurate energy estimation tool,Proceedings of 38th Design Automation Conference,pp.340-345,June 2000
  • 3[3]D Brooks,P Bose,V Srinivasan,M K Gschwind,P G Emma,and M G Rosenfield.New methodology for early-stage,microarchitecture-level power-performance analysis of microprocessors,IBM Journal of Research & Development,September/November 2003,Vol.47 No.5/6,pp.653-670
  • 4[4]Hang-Sheng Wang; Xinping Zhu; Li-Shiuan Peh; Malik,S.Orion:a power-performance simulator for interconnection networks.35th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-35),Nov.2002
  • 5[6]J.Li,J.Martinez,and M.Huang.The thrifty barrier:Energy efficient synchronization in shared-memory multiprocessors.In Proceedings of HPCA,2004,pp.14-23
  • 6[7]The official ACPI specification,Revision 3.0b,October 10,2006,http://www.acpi.info/
  • 7[9]R.Kumar,K.I.Farkas,N.P.Jouppi,P.Ranganathan,and D.M.Tullsen.Single-ISA heterogeneous multi-core architectures:The potential for processor power reduction.In Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture,2003,pp.81-92
  • 8[10]Anoop Iyer,Diana Marculescu.Power and Performance of Globally Asynchronous Locally Synchronous Processors.In Proceedings of ISCA,2002,pp.158-168
  • 9[11]W.J.Dally,B.Towles,"Route Packets,Not Wires:On-Chip Interconnection Networks," in Proceedings of the 38th Design Automation Conference,Las Vegas,NV,June 2001,pp.684-689
  • 10[12]C.Liu,A.Sivasubramaniam,and M.Kandemir,Organizing the Last Line of Defense before Hitting the Memory Wall for CMPs,10th IEEE Symposium on High-Performance Computer Architecture,Feb.2004,pp.176-185

共引文献1

同被引文献68

  • 1高明伦,杜高明.NoC:下一代集成电路主流设计技术[J].微电子学,2006,36(4):461-466. 被引量：31
  • 2Fayez Gebali, Haytham Elmiligi, M. Watheq E1-Kharashi, Networks-on-chips : theory and practice,2009.
  • 3David E.Culler, Jaswinder Pal Singh,Anoop Gupta, Parallel Computer Architecture,2002,58-73.
  • 4骆祖莹.芯片功耗与工艺参数变化:下一代集成电路设计的两大挑战[J].计算机学报,2007,30(7):1054-1063. 被引量：17
  • 5Hu J, Marculescu R. Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints. [C]. Proc. DATE, Feb 2004, 234-239.
  • 6www.itrs.net, International Technology Roadmap for Semiconductors, 2010.
  • 7Tile64 Processor Product Brief, www.tilera.com /products/processors.
  • 8S. Vangal et al., "An 80-tile 1.28TFLOPS networkon-chip in 65 nm CMOS," in Proc. Solid-State Circuits Conf., Feb. 2007, pp. 98-589.
  • 9杜高明.MPSoC-NoC多核体系结构及原型芯片实现技术研究,合肥工业大学博士学位论文.
  • 10J. Nurmi, H. Tenhunen, J Interconnect-eentric design NoC," Kluwer Academic. Isoaho, and A. Jantsch, for advanced SoC and.

引证文献11

二级引证文献14

电子产品世界
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