一种高效RS编解码器的FPGA实现

Implementation of High Efficiency RS Codec Based on FPGA

提出了一种实现复杂度低、高效率的RS(204,188)编解码器的FPGA实现电路。整个FPGA设计分为RS编码器、Horner准则的伴随式计算、改进的BM算法、Chien搜索求根和Forney算法求差错幅值等5个模块,同时,总体电路采用了pipeline结构,有效提高了译码速率。选用Xilinx公司的Spartan3E系列XC3S500E芯片,译码时延242个时钟周期,使用FPGA资源186000门,译码性能与理论值一致,已用于特定无线图像传输系统。

A low complexity and high efficiency FPGA circuit of RS （204,188） encoder and decoder is put forward. The design is divided into five modules： RS encoder module, Homer criteria with computing module, an improved algorithm of the BM mod ule, Chien search rooting module, Forney algorithm for error amplitude module. At the same time, the whole circuit uses a pipeline structure to raise the rate of decoding effectively. The design is implemented on XC3S500E chips of Xilinx Spartan3E family, with 242 clock cycles of decoding delay, and using 186 000 gates. The decoding performance agrees with the theoretical value and it has already used in a special wireless image transmission system.