摘要
在AVS标准中的插值算法采用分像素提高视频解码的清晰度,也是解码端主要的访存和计算瓶颈。为了得到分像素位置的像素值,需要参考其周围相邻的像素值;针对亮度和色度插值设计了一种基于流水线的并行架构,计算出不同位置上的分像素值,提高了解码系统的运算速度,与其他设计完成的解码器模块配合,在FPGA上实现AVS高清实时解码。
The interpolation of AVS adapts sub-pixel to improve the definition of video decoder, and also is the computing and memory access bottleneck of video decoder. In order to compensate sub-pixel displacements, the sub-pixel has to reference pixel around it. This paper proposes a parallel implementation based on pipeline for the luminance and chroma interpolation, which improves the speed of decoding system. At the same time, this part with others of decode system can perform high-definition real-time decoding of AVS on FPGA.
出处
《火力与指挥控制》
CSCD
北大核心
2008年第12期140-143,共4页
Fire Control & Command Control
基金
宁波市高新技术计划基金资助项目
