基于ADC的时钟jitter测试平台的研究

A clock jitter generation and measurement platform

本文实现了一种利用高速模数转换器(ADC)采样测量时钟jitter的硬件测试平台。文中针对高速、高分辨ADC的特性,导出时钟Jitter对输出码密度的影响,根据这层关系可以反推出时钟Jitter的大小。同时介绍了如何在硬件上产生高速、可以控制的时钟jitter。最后通过ModelSim和Matlab对这个平台进行仿真分析,结果表明这种方法不需要高性能仪器,且具有高分辨和低时耗等特点。

In this paper, we propose a hardware-based platform for clock jitter generation and measurement based on high-speed ADC. The effects of jitter on high-speed and high-precision ADC＇s output are introduced, as the theoretical basis of jitter deducing. The method of generating high-speed and controllable clock jitter is also included. Emulation of this platform using ModelSim and Matlab shows, that it takes only a small measuring time, and can achieves high precision without high perfomance devices.