期刊文献+

输入队列交换的公平可扩展调度系统

Fair scalable scheduling architectures for input-queued switches
下载PDF
导出
摘要 提出了一种基于输入队列交换的公平可扩展网络调度系统FSSA。通过将若干个容量较小的调度器合理连接并使其协同工作,构成多端口大容量网络交换调度系统,解决了单个调度器容量和端口数受集成电路工艺限制的问题。FSSA不仅速度高、规模可扩展而且易于硬件实现。环型连接、管线工作及公平调度技术的采用使FSSA在性能方面得到了进一步优化。仿真结果显示,FSSA的性能可与基于iSLIP、DSRR等算法的单片调度器相比拟,尤其在流量较大时,FSSA的性能明显优于单调度器性能。 This paper presents a fair scalable scheduling architecture (FSSA) for input queued switches. In the FSSA, a large scheduler is realized by connecting several small scheduling devices and making them work in fair pipeline scheduling. The important feature of this architecture is that it can be configured as a large scheduler with high performance but without the capacity limitations due to the size of monolithic scheduling device, The simulation results show that the performance of the FSSA is better than or very close to that of other typical scheduling algorithms under high traffic load.
出处 《电路与系统学报》 CSCD 北大核心 2008年第6期40-46,共7页 Journal of Circuits and Systems
基金 国家自然科学基金资助项目(60472057)
关键词 通信 输入队列交换 调度器 可扩展 下一代网络 communication input-queued switch scheduler scalable next-generation network
  • 相关文献

参考文献9

  • 1N McKeown. iSLIP: A scheduling algorithm for input-queued switches [J]. IEEE Trans. On Networking, 1999, 7(2): 188-201.
  • 2A Mekkittikul, N McKeown. Achieving 100% throughput in an input-queued switch [J]. IEEE Trans. On Communication, 1999, 47(8): 1260-1267.
  • 3P Giaccone, B Prabhakar, D Shah. Towards simple, high-performance schedulers for high-aggregate bandwidth switches [A]. IEEE INFOCOM [C]. 2002,
  • 4PMC datasheet. Enhanced TT1 Chip Set. http://www.PMC-serria.com.
  • 5Masatoshi Kumagai, Satoshi Nojima and Hiroshi Tomonaga. IP Router for next-generation network [J]. FUJITSU Science Tech. J., 2001, 37(1): 31-41.
  • 6孙志刚,苏金树,卢锡城.高效的Crossbar仲裁算法——ISP[J].计算机学报,2000,23(10):1078-1082. 被引量:12
  • 7Ying Jiang, Mounir Hamdi. A fully desynchronized round-robin matching scheduler for a VOQ packet switch architecture [A]. IEEE Workshop on HPSR [C]. 2001. 407-411.
  • 8L Tassiulas. Linear complexity algorithms for maximum throughput in radio networks and input queued switches [A]. IEEE INFOCOM98 [C]. 1998, 2(1): 533-39.
  • 9Jing Liu, Mounir Hamdi, et al. Scalable scheduling architecture for high-performance crossbar-based switches [A]. IEEE Workshop on HPSR [C]. 2004, 104-110.

二级参考文献6

  • 1Craig Partridge et al.A 50-Gbps IP router[].IEEE ACM Transactions on Networking.1998
  • 2Richard,Dimitrio.Two-dimensional round-robin schedulers for packet switches with multiple input queues[].IEEE ACM Transactions on Networking.1994
  • 3McKeown N.Scheduling algorithms for input -queued switches[Ph D dissertation][]..1995
  • 4McKeown N,Izzard M.The tiny tera: A packet switch core[].IEEE Micro Magazine.1997
  • 5Keshav S,Sharma R.Issues and trends in router design[].IEEE Communications Magazine.1998
  • 6Anderson,Owicki.High speed switch scheduling for local area networks[].ACM Transactions on Computer Systems.1993

共引文献11

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部