基于FPGA IP核的中频接收与脉压设计

Digital IF Receiving and Pulse Compression Based on FPGA IP Core

随着FPGA(现场可编程门阵列)在规模和性能上得到显著增强,意味着FPGA能够代替DSP或者某些专用芯片,实现数字信号处理中某些运算密集型的算法,并且能够获得更高的性能。在分析数字正交检波技术和数字脉压技术的基础上,介绍了一种基于FPGA芯片的数字中频接收机设计方案,该接收机能够实现线性调频信号的数字下变频和数字脉压功能。该设计采用FPGA IP核来实现,另外,还介绍了主要IP核的特性,并提出了一些简化方法,用以节约FPGA内部资源提高效率。

Modem FPGAs are improved in their size and performance remarkably, which means, instead of DSP or some special chips, FPGA can implement some computationally intense algorithm and achieve higher performance. Based on technique of digital orthogonal detection and digital pulse compression, a design of a digital IF receiver is introduced in this paper, which is based on FPGA IP core and can be used for DDC and some preprocessing of chirp signal. Features of main IP core are presented, and some special methods are proposed at the same time, so as to make this design efficient.