应用于DVB-T的0.18μm CMOS工艺数字可编程分频器芯片设计

Digital Programmable Frequency Divider in Frequency Synthesizer for PLL Based on 0.18 μm CMOS Technology

介绍了用于DVB-T(地面数字视频广播)收发机的频率综合器中可编程分频器的设计。该分频器可实现926～1387范围的分频比,并用改进的分频算法使分频输出波形的占空比更加理想。本设计采用SMIC0.18μmCMOS工艺标准单元的半定制设计方法,按标准的数字集成电路设计流程进行设计,包括Verilog代码编写、逻辑综合、版图规划、布局布线、后端时序仿真分析等过程。后仿真结果表明该分频器功能正确,分频范围宽,利用改进的分频算法改善了分频输出波形的占空比。

A digital CMOS programmable frequency divider used in frequency synthesizer for Digital Video Broadcasting Terrestrial （DVB-T） transceiver was proposed. The frequency divider achieves a dividing ratio ranging from 926 to 1387. Better duty cycle of the output wave form is realized by a improved RTL coding method . Standard ASIC design flows , such as verilog RTL coding , logic synthesizing , layout planning , detailed routing, post-layout simulation are carrized out. The proposed structure is implemented and simulated using a standard SMIC 0.18 μm CMOS logic processing model. Simulation results show that the proposed frequency dividing works correctly with a wider divide ratio range and has better duty cycle of the output waveform.