期刊文献+

NoC架构片上多处理器系统性能探索 被引量:1

Performance Exploring of NoC Based Multi-Processor System-on-a-Chip
下载PDF
导出
摘要 采用SystemC建模和仿真环境建立了一款NoC系统级仿真平台,设计了3个实验分别用于建模3种典型应用(低计算/通信比、高计算/通信比和非独立任务),以定量模拟的方法对NoC架构MPSoC性能进行了详细的调研,并将其结果与总线架构MPSoC进行了对比分析.实验结果显示:NoC系统加速比与处理器数目呈线性关系,不受规模的影响,而总线系统则明显受到处理器数目的限制;共享存储资源成为NoC系统性能提升的限制,但可以通过采用分布式存储策略得到解决,而总线系统却无法克服其共享总线通信瓶颈.因此,在系统规模较大(N>12)时推荐采用NoC体系结构. In this paper, a NoC system level simulation platform is setup first, then three kinds of tasks are designed to run on this platform and experimental results are analyzed and compared with that of bus-based MPSoC; lastly. It is shown that the speedup of NoC system is in linear with the number of integrated processors, which proves performance of NoC system is not restricted by processors number as bus-based system does; shared memory resources have important influences on NoC; system performance, but it will not become a bottleneck by utilizing distributed shared memory solution. So NoC is recommended when the size of target system is large (N〉12).
出处 《微电子学与计算机》 CSCD 北大核心 2009年第1期63-66,共4页 Microelectronics & Computer
基金 国家自然科学基金项目(90307011 60576034) 国家"八六三"计划项目(2008AA01Z135)
关键词 NOC 总线 片上多处理器系统 加速比 单核效率 NoC bus MPSoC speedup efficiency per core
  • 相关文献

参考文献6

  • 1Pasricha S, Bozorgzadeh N, Ben - Romdhane E, et al. Floorplan-aware automated synthesis of bus-based communication architectures[C]//Proceedings of the 42nd annual conference on Design automation 2005. Anaheim, California, USA: IEEE, 2005 : 565 - 570.
  • 2Paulin Pierre G, Pilkington Chuck. Parallel programming models for a muhiprocessor SoC platform applied to networking and multimedia [ J ]. IEEE Transactions on very large .scale integration(VLSI) Systems, 2006, 33 (7) : 667 - 680.
  • 3Arteris. A comparison of network - on - chip and busses [EB/OL]. [2005 - 12 - 10]. http://www. arteris. com.
  • 4杨盛光,李丽,徐懿,张宇昂,张冰.基于总线共享架构的片上多处理器系统性能探索[J].微电子学与计算机,2007,24(12):16-19. 被引量:3
  • 5陈绍贺,赵明,王京.基于SystemC的片上系统设计[J].微电子学与计算机,2005,22(4):51-52. 被引量:11
  • 6Sudeep Pasricha, Nikil Dutt, Mohamed Ben - Romdhane. Extending the transaction level modeling approach for fast communication architecture exploration [ C ]// DAC' 04. San Diego, California, USA: IEEE, 2004:113-118.

二级参考文献12

  • 1王峥,李德识,曹阳,张俊新.基于SystemC的AMBA总线模型的构建与验证[J].微电子学与计算机,2004,21(12):1-3. 被引量:3
  • 2陈绍贺,赵明,王京.基于SystemC的片上系统设计[J].微电子学与计算机,2005,22(4):51-52. 被引量:11
  • 3Open SystemC Initiative. SystemC 2.0 User Guide. http: //www.systemc.org.
  • 4Kalavade A, Lee E A. Global Criticality/local Phase Driven Algorithm for the Constrained Hardware/ Software Partitioning Problem. In Proc 3nd IEEE Int. Workshop. Hardware/Software Co-design, Sept. 1994: 42~48.
  • 5Jantsch A, Ellervee P, Hemani A. Hardware/Software Partitioning and Minimizing Memory Interface Traffic. In.IEEE/ACM Proc. European Conf. Design Automation(EuroDAC), Sept. 1994: 220~225.
  • 6R Emst, J Henkel, T Benner. Hardware-software cosynthesis for microcontrollers. IEEE Design and Test of computers,Dec.1993, 10(4): 64~75.
  • 7Ken Chapman. PicoBlaze 8-bit Microcontroller for Virtex-E and Spartan-Ⅱ/ⅡE Devices. Xilinx, XAPP213 ,February,2003.2.
  • 8Poletti F, Bertozzi D, Benini L, et al. Performance analysis of arbitration policies for SoC communication architectures [A]. Design Automation for Embedded Systems [C]. 2003: 189-210
  • 9Charles Bo-Cheng Lai, Patrick Schaumont. Energy and performance analysis of mapping parallel multithreaded tasks for an on-chip multi-processor system [C]. Proceedings of the 2005 International Conference on Computer Design, California, 2005
  • 10Pierre G Paulin, Chuck Pilkington. Parallel programming models for a multiprocessor SoC platform applied to networking and Multimedia [J]. IEEE Transacctions on Very Large Scake Integration (VLSI) Systems, July 2006, 33 (7): 667-680

共引文献12

同被引文献5

  • 1Jantsch A, Tenhunen H. Networks- on -chip[M]. USA: Kluwer, 2003.
  • 2Kumar S, Jantsch A, Millberg M, et al. A network on chip architecture and design methodology [ C]//Proceedings of the IEEE Computer Society Annual Symposium on VLSI. PA, USA:IEEE press, 2002:105 112.
  • 3Benini L, Micheli G D. Networks on chips: a new SoC paradigm[ J ]. IEEE Computer, 2002, 35 ( 1 ) : 70 - 78.
  • 4Goossens K, Meerbergen J, Peeters A, et al. Networks on silicon: combining best - effort and guaranteed services[C]//Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition (DATE. 02). Frarce: Paris, 2002: 1 - 3.
  • 5丁帅,吴宁,葛芬,王祺.片上网络路由单元的系统级建模研究[J].微电子学与计算机,2009,26(1):93-96. 被引量:10

引证文献1

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部