AVS高清视频变长码解码器算法与电路实现

An Algorithm and Architecture of VLD for AVS HDTV Application

提出一种适用于AVS高清视频解码的变长码解码结构.该结构在一个周期内完成一个指数哥伦布码的解码、查表、语法元素计算和更新码表的操作;通过组合逻辑映射查表,完全避免了对存储器的访问,大大减少面积;采用流水线技术计算输出结果,提高系统性能.对该模块进行了仿真和综合,在0.18μm工艺下,频率为176MHz,面积为8k等效逻辑门.

This paper presents a novel VLD decoder for AVS. It finishes Exp-Golomb code decoding, looking up table, calculating symbols and updating table in one cycle, it uses combinational logic looking up table to avoids memory access and decreases area greatly, it uses pipeline technique to improve performance. Simulate this module and implement use 0.18um , the frequency reaches 176MHz and the circuit costs 8k Gates.