一种适用于RFID标签芯片的AES算法结构设计

An Optimized Architecture Design of AES for RFID Tag

针对当前AES算法不能满足超高频RFID标签芯片小面积、高效率的要求,重新构造AES算法的轮变换,实现多个运算步骤同步完成,提高了算法执行效率;用基于有限域的逻辑运算代替S盒查找表,降低芯片面积,满足了超高频RFID系统安全性要求.

The AES （Advanced Encryption Standard） algorithm can not meet the small-area high-performance requirement of UHF RFID tag. We introduce a new architecture which implements the first three steps in a single step by adjusting and reordering the four functional steps in each round function. The architecture uses the finite field based logic operation instead of the Sbox to reduce the chip area. The result shows that the new architecture can satisfy the security requirement of RFID system.