摘要
设计了一个高速(2,1,6)Viterbi译码器,通过采用并行基-4结构和比特级进位保存算法(Carry-Save Arith-metic),改进了Viterbi算法中加-比-选单元(Add-Compare-Select Unit)的结构,消除传统行波进位加法(Ripple-CarryAdder)结构中的进位链,缩减了Viterbi译码器的关键路径,从而提高译码速度,可用在中、高速数字通信的不同应用场合中.
A high-speed (2,1,6) Viterbi decoder is presented in this paper, which is based on parallel Radix-4 architecture and bit-level Carry-Save algorithm. In this design architecture of Add-Compare-Select unit in Viterbi algorithm is improved, the carry chain of traditional Ripple-Carry Adder is eliminated. Therefore, the critical path of Viterbi decoder is shortened; a high decoding throughput achieved. The proposed Viterbi decoder has great chance to be applied to different digital communication systems that need high throughput.
出处
《微电子学与计算机》
CSCD
北大核心
2009年第1期109-112,117,共5页
Microelectronics & Computer