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高速VITERBI译码器的研究与设计 被引量:1

Study and Implementation of a High-Speed Viterbi Decoder
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摘要 设计了一个高速(2,1,6)Viterbi译码器,通过采用并行基-4结构和比特级进位保存算法(Carry-Save Arith-metic),改进了Viterbi算法中加-比-选单元(Add-Compare-Select Unit)的结构,消除传统行波进位加法(Ripple-CarryAdder)结构中的进位链,缩减了Viterbi译码器的关键路径,从而提高译码速度,可用在中、高速数字通信的不同应用场合中. A high-speed (2,1,6) Viterbi decoder is presented in this paper, which is based on parallel Radix-4 architecture and bit-level Carry-Save algorithm. In this design architecture of Add-Compare-Select unit in Viterbi algorithm is improved, the carry chain of traditional Ripple-Carry Adder is eliminated. Therefore, the critical path of Viterbi decoder is shortened; a high decoding throughput achieved. The proposed Viterbi decoder has great chance to be applied to different digital communication systems that need high throughput.
出处 《微电子学与计算机》 CSCD 北大核心 2009年第1期109-112,117,共5页 Microelectronics & Computer
关键词 VITERBI译码器 进位保存算法 加-比-选 高速 Viterbi decoder carry-save algorithm add-compare-select unit high-speed
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参考文献8

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共引文献9

同被引文献6

  • 1Sun Fei, Zhang Tong. Low-power state-parallel relaxed adaptive viterbi decoder[J]. IEEE Transactions on Cir- cuits and Systems Ⅰ, 2007,54(5): 1060- 1068.
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  • 6李刚,黑勇,仇玉林.MB-OFDM UWB系统中高吞吐率Viterbi译码器的实现[J].微电子学与计算机,2008,25(4):18-21. 被引量:2

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