基于FPGA的GPS接收机的核心模块设计

The core module of GPS receiver based on FPGA

运用Quartus II对GPS接收机进行了数据采集(COM-R)、存储器(memory)、写地址控制(writer)、接收数据处理(reader)等核心模块的FPGA设计和仿真,结果表明各模块设计合理.

Quartus II was used to for FPGA designing and simulating in data acquisition （COM.R）,memory （memory）, write address control （writer）, and received data processing （reader） of core roodules of GPS receiver. The simulation results indicated that the module designs were reasonable and correct.