基于CPLD的面阵CCD驱动时序发生器设计

Design of driving schedule generator for area array CCD based on CPLD

CCD技术在图像传感和非接触测量领域发展前景广阔。CCD驱动时序的产生是其应用的关键。在分析Sony公司的ICX205AL型面阵CCD器件驱动时序关系的基础上,设计了其驱动时序发生器。选用复杂可编程逻辑器件(CPLD)作为硬件设计平台,使用Verilog硬件描述语言对该驱动时序发生器进行了硬件描述。所设计的驱动时序发生器采用ispLEVER软件进行了功能仿真,并针对Lattice公司的可编程逻辑器件LC4256V-75T100I进行了硬件适配。实际测试表明,所设计的驱动时序发生器能够满足面阵CCD的驱动要求,实现了设计目的。

The technology of CCD has a bright prospect in image transducing and noncontact measuring. The generation of CCD＇s driving schedules is the key of CCD＇s application. Driving schedules of ICX205AL area array CCD produced by Sony Corporation are examined in detail, based on which, driving schedule generator is designed. CPLD is chosen as the hardware design platform, and the driving schedule generator is described with Verilog hardware description language. The designed generator is successfully fulfilled function simulation with ispLEVER software and fitted into LC4256V-75T100I which is a CPLD product made by Lattice Corporation. Experiments show that the designed generator is suitable for the driving of area array CCD with the function being realized.