一种基于FPGA的曼彻斯特编译码电路设计

Manchester Encoding and Decoding Circuit Based on FPGA

运用VHDL硬件描述语言以及Max-plus软件平台,采用超前滞后型全数字锁相环提取位同步时钟的方法,设计了一种基于全数字锁相环的曼彻斯特编译码电路,给出了详细的设计过程和波形仿真,并在GW48-CK实验平台上进行了下载验证.

Applying the hardware description language VHDL and the software platform Max-plus, a Manchester coding and decoding circuit is designed based on LL-ADPLL which refines bit synchronized clock signal. The design process and waveform simulation are given; and they are testified by downloading in GW48- CK experimental platform.