期刊文献+

片上Trace辅助的嵌入式多核程序分析与调优 被引量:1

Analyzing and Optimizing Embedded Multi-Core Programs with On-Chip Trace
下载PDF
导出
摘要 YHFT-QDSP是一款多核处理器,TraceDo是其实时片上追踪调试系统。本文首先将串行二维快速傅立叶变换算法(2D-FFT)并行化,映射于该多核处理器;并基于可视化的TraceDo系统,从多核程序同步及核间数据传输两个方面深入分析了并行2D-FFT程序行为;而后提出并实现了两种性能优化(调优)方案。实例研究表明,TraceDo系统可有效地提高嵌入式多核程序的开发效率。 YHFT-QDSP is a multi-core processor and TraceDo is its on-chip trace system supporting multi-core and real- time debugging. The 2D-FFT algorithm is parallelized in YHFT-QDSP, and is analyzed and optimized with the TraceDo system. This case study shows TraceDo is able to help develop embedded multi-core programs efficiently.
出处 《计算机工程与科学》 CSCD 北大核心 2009年第1期113-116,共4页 Computer Engineering & Science
基金 国家自然科学基金资助项目(60473079) 教育部高等学校博士学科点专项科研基金资助项目(20059998026)
关键词 多核处理器 程序优化 片上追踪 并行算法 二维快速傅立叶变换 multi-core processor program optimization on-chip trace parallel algorithm 2D-FFT
  • 相关文献

参考文献6

  • 1陈书明,李振涛,万江华,胡定磊,郭阳,汪东,扈啸,孙书为.“银河飞腾”高性能数字信号处理器研究进展[J].计算机研究与发展,2006,43(6):993-1000. 被引量:29
  • 2Hopkins A B T, McDonald Maier K D. Debug Support Strategy for Systems-on-Chips with Muhiple Processor Cores[J]. IEEE Trans on Computers, 2006,35(2):174-184.
  • 3扈啸,陈书明.嵌入式处理器片上Trace实时调试结构技术综述[C].中国计算机学会第十届计算机工程与工艺学术年会,桂林,2006.
  • 4IEEE-ISTO 5001^TM-2003, The Nexus 5001 Forum^TM Standard for a Global Embedded Processor Debug Interface v2.0 [EB/OL]. [2007-04-05]. http://www.nexus5001.org/ standard2.html.
  • 5Hu Xiao, Ma Pengyong, Chen Shuming,et al. TraceDo: An On-Chip Trace System for Real-Time Debug and Optimization in Multiprocessor SoC [C]//Proc of ISPA'06, 2006.
  • 6王耀华.FFT算法在异构多核DSP上的映射:[学士学位论文][D].长沙:国陶防科学技术大学计算机学院,2007.

二级参考文献27

  • 1胡定磊,陈书明.低功耗编译技术综述[J].电子学报,2005,33(4):676-682. 被引量:11
  • 2Jennifer Eyre, Jeff Bier. The evolution of DSP processors, http://www. BDTI. com, 2000
  • 3DSP adapt to new challenges, http://www. BDTI.com, 2003
  • 4A BDTI analysis of Texas Instrument TMS320C64x. http://www. BDTI. com, 2003
  • 5ADSP-BF531/ADSP-BF532/ADSP-BF533 Datasheet. Analog Devices, Inc. http://www. analog.com, 2004
  • 6MSC8126 Reference Guide. Freescale Semiconductor, http://www. freescale.com, 2004
  • 7Piia Simonen, Ilkka Saastamoinen, Mika Kuulusa, et al.Advanced instruction set architectures for reducing program usage in a DSP processor. The first IEEE Int'l Workshop on Electronic Design, Test and Applications, Christchurch, New Zealand, 2002
  • 8Paul M Heysters, Gerard J M Smit. Mapping of DSP algorithms on the MONTIUM architecture. In: Proc. 17th Int'l Parallel and Distributed Processing Symposium. Los Alamitos, CA: IEEE Computer Society Press, 2003
  • 9Christopher Pretty, J Geoffrey Chase. Reconfigurable DSP's for efficient MPEG-4 video and audio decoding. The First IEEE International Workshop on Electronic Design, Test and Applications, Christchurch, New Zealand, 2002
  • 10Paolo Gai, Luca Abeni, Giorgio Buttazzo. Multiprocessor DSP scheduling in system on-a-chip architectures. The 14th Euromicro Conf. Real-Time Systems, Vienna, Austria, 2002

共引文献28

同被引文献4

引证文献1

二级引证文献5

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部