一种图形光栅的硬件实现算法

A Hardware Algorithm for Graphics Rasterizer

提出了一种面向嵌入式平台的图形光栅的硬件实现算法。将三角面包围盒内的像素分成多个规则像素块,在像素块基础上进行扫描转换和像素插值以及透视校正。在对算法做了大量优化后,用FPGA(现场可编程门阵列)对算法进行了实现和验证。与传统的光栅算法相比,提出的算法提高了像素命中率,减小了计算复杂度,降低了硬件成本。验证结果表明,算法渲染的图形质量达到OpenGLES1.1渲染效果;在一般场景下的渲染速度达到30帧/秒,满足实时渲染要求;在XilinxFPGAVertex2Pxc2vp30-7ff89上的综合资源为5545个Slice,硬件消耗较小。

In this paper, a hardware algorithm for graphics rasterizer on embedded platform is presented. By dividing the pixels in the triangle＇s bounding box into a number of regular tiles, the algorithm do the scan conversion, pixel interpolation and projective correction on the basis of tile architecture. After a lot of optimization, the algorithm is implemented and tested on FPGA. As compared with the traditional algorithm, the algorithm presented in this paper has increased the pixel hit rate, and reduced the computational complexity, as well as effectively reduced the hardware cost. Testing results show that, the quality of the algorithm＇s rendered images has reached the level of OpenGL~ ES 1.1. In general scene, the rendering speed reached 30 fps, meeting the requirements of real-time rendering. In terms of the synthesized hardware resources, it is small within 5 545 slices on Xilinx FPGA Vertex2P xc2vp30-7ff89.