摘要
研究了采用译码的分段梯形电阻网络技术制作的高速12位CMOS电流型D/A转换器。将常规的R-2R电阻网络和译码的权电阻网络相结合,解决了常规CMOSD/A转换器必须采用精密R-2R梯形电阻网络的问题,降低了对电阻精度匹配的要求。同时,为了使D/A转换器具有灵活的外围应用,专门设计了微处理器接口、基准发生器和量程选择电阻。未修调的实验样品的线性误差小于0.05%,建立时间为400ns。
A high speed 12 bit CMOS current mode digital to analog converter based on segmented resistor ladder networks for decoding has been developed Combined with R 2R resistor ladder and weighted resistor networks for decoding, it eliminates the need for a precise R 2R ladder network that is necessary for a conventional CMOS D/A converter It also lowers the requirement for match of resistor’s accuracy An interface to microprocessor, reference generators and resistors for range selection are designed to make the D/A converter more flexible in peripheral applications For the sample circuit without trimming, a linear error less than 0 05% and a settling time of 400 ns have been obtained
出处
《微电子学》
CAS
CSCD
北大核心
1998年第1期45-49,共5页
Microelectronics
关键词
模拟集成电路
电阻网络
D/A转换器
DSP
Analog IC, Digital to analog converter, Ladder network, Digital signal processing