高性能BiCMOS制造技术及I/O电路优化

High Performance BiCMOS Fabrication Technologyand I/O Circuit Optimization

本文报导一套先进的ＢｉＣＭＯＳ集成电路制造技术。建立在ＣＭＯＳ工艺基础上的ＢｉＣＭＯＳ制造工艺，增加了双埋层、２．５微米本征外延层、双阱、基区、多晶硅发射区、深集电区和平坦化双层金属布线等工艺技术。器件性能测试和扫描电镜检查结果表明，双极器件和ＭＯＳ器件性能优良，ＢｉｃＭＯＳ器件的抗锁定性能比ＣＭＯＳ器件提高了一个数量级。优化设计了高性能该电路。当负载电容为２．０ｐＦ时，该电路的延迟时间为１．２ｎｓ，ＢｉＣＭＯＳ宏单元的传输速度比同类ＣＭＯＳ电路有所提高，这套制造技术适合于１．２～２．０μｍ ＢｉＣＭＯＳ集成电路的制造。

A high performance BiCMOS fabrication technology is presented. The high performance BiCMOS process is realized by adding the following process steps: twin buried layers, 2.5μm intrinsic epitaxial layer, twin wells, base, polysilicon emitter and deep collector. Satisfactory device profiles and test results of device electrical performance indicate that both advantages of bipolar and CMOS devices are achieved by applying this BiCMOS technology. The latch-up effect in BiCMOS is reduced to one-tenth of that in CMOS. High performance BiCMOS I/O circuit has been developed through simulation and fabrication. The delay time of BiCMOS I/O circuit is 1.2 ns with a 2.0 pF load capacitance. The average gate delay time of BiCMOS macrocells is about half of that of CMOS and the average gate access speed of BiCMOS is increased. This technology can be applied to 1.2μm to 2.0μm BiCMOS integrated circuit fabrication.