基于FPGA的数字锁相环设计

Design of Digital Phase-Locked Loop Based on FPGA

介绍了一种应用VHDL语言设计数字锁相环的设计方法,阐明其基本工作原理和设计思想,给出了系统主要模块的设计过程和仿真结果;用可编程逻辑器件FPGA予以实现。该方案提高了DPLL的快速锁定性能,同时保证了锁定精度。

Digital phase - locked Loop （DPLL） technology will be used widely. This paper has proposed a methodology of designing DPLL,systematically states its operational principle which is followed by the designing processes and simulating results of the main modules. This methodology, based on VHDL technique, can be implemented by field programmable logic array（FPGA）.