摘要
为了推动音视频编码标准(AVS)解码芯片产业的发展,提出了一种基于AVS标准的帧间预测亮度插值电路的硬件结构。该设计将像素点按位置的不同分为三层,并采用了不同的流水线结构予以实现,充分利用了像素点之间的复用情况,兼顾处理速度和实现代价两方面考虑,硬件实现效率较高。满足了硬件资源以及系统时钟频率的要求。
To promote the development of the audio video coding standard （AVS） chip industry, an inter prediction Iuminance interpolation circuit architecture for AVS is proposed in this paper. The pixel points are divided into three layers according to their different positions. And the luminanee interpolation of each pixel is implemented by different pipeline architectures. The design takes full advantage of the reusable pixel points. This architecture considers both proper work frequency and hardware cost , with high hardware implementation efficiency. The hardware resource and the clock frequency of system can be satisfied.
出处
《计算机技术与发展》
2009年第1期190-192,196,共4页
Computer Technology and Development
关键词
AVS
帧间预测
亮度插值
硬件架构
AVS
inter prediction
luminance interpolation
VLSI architecture
