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基于超大规模FPGA的FFT设计与实现

Design of FFT operation based on ultra large scale FPGA
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摘要 在宽带数字接收机中,需要对数字检波输出的信号流进行实时FFT运算。提出了一种用于宽带数字接收机的基于Xilinx的Virtex-IV芯片的高速FFT的设计与实现方法,采用了多级串行流水线结构及优化的数据存取方式,设计出用单片FPGA实现了2048点实数的FFT方案。其完成2048点FFT的时间约为4.57μs,能很好地满足系统处理的实时性要求,在工程实践中有很大的应用前景。 The speed of carrying out a FFT operation has been improved due to the using of ultra very large scale Field Programmable Gate Array(FPGA). It is needed to carry out a FFT operation on the digital signal stream which is outputted by a digital detector of a wide band digital receiver. The paper studied a method of high speed FFT operation based on the Xilinx Virtex- IV FPGA, the module of FFT operation is used in a wideband digital receiver. A structure of multilevel serial pipeline is brought forward, and the mode of reading and writing date is optimized too. Based on the method, a FFT operation on 2 048 points real can be carried out on a single piece of FPGA. The time of the FFT operation need is 4.57 μs, which can meet the real-time processing of a wide band receiver.
出处 《电子技术应用》 北大核心 2009年第1期109-112,共4页 Application of Electronic Technique
关键词 FPGA FFT算法 数字接收机 多级流水线 FPGA FFT operation digital receiver multilevel serial pipeline
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  • 1余官定,张朝阳,仇佩亮.一种自适应正交频分复用系统的子载波分配算法[J].浙江大学学报(工学版),2004,38(9):1112-1116. 被引量:5
  • 2潘文,钱俞寿,周鹗.基于加窗插值FFT的电力谐波测量理论──(Ⅰ)窗函数研究[J].电工技术学报,1994,9(1):50-54. 被引量:178
  • 3JamesTsui 杨小牛 陆安南 金飚译.宽带数字接收机[M].电子工业出版社,2002,10..
  • 4CIMINI L J. Analysis and simulation of a digital mobile channel using orthogonal frequency division multiplexing[J]. IEEE Transactions on Communications, 1995, 33:665 - 675.
  • 5CHUANG J,SOLLENBERGER N. Beyond 3G: Wideband Wireless Data Access Based on OFDM and Dynamic Packet Assignment[J]. IEEE Communications Magazine, 2000, 38: 78-87.
  • 6ZOU W Y, WU Yi-yan. COFDM: An overview [J].IEEE Transaction on Broadcasting, 1995, 41 ( 1 ): 1 - 8.
  • 7BI Guo-an, JONES E V. A pipeline FFT processor for word-sequential data[J]. IEEE Transaction on Acorntics, Speech and Signal Processing, 1989, 37 (12):1982 - 1985.
  • 8WOLD E H, DESPAIN A M. Pipeline and parallel pipeline FFT processor for VLSI implementation[J].IEEE Transaction on Computer, 1984, 33 (5): 414 -426.
  • 9SWARTZLANDER E E, YOUNG W K W, JOSEPH S J. A radix 4 delay commutator for fast Fourier transform processor implementation [J]. IEEE Journal of Solid-State Circuits, 1984, SC-19 (5) : 702 - 709.
  • 10CHANG Yun-nan, PARPHI K K. An efficient pipelined FFT architecture [J]. IEEE Transaction on Circuits and Systems-Ⅱ:Analog and Digital Signal Processing,2003,50 (6) : 322- 325.

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