耦合结构高分辨率电荷按比例缩放DAC的分析

Analysis of Coupled High-resolution Charge Scaling DAC

耦合结构高分辨率电荷按比例缩放DAC占用面积小,功耗低,然而其互连结点之间的寄生电容影响了它的线性.介绍了耦合结构高分辨电荷按比例缩放DAC级间耦合电容值的设计方法,讨论了寄生电容对DAC精确度的影响.用两种不同的理论模型分析了电容轨迹误差对DAC精确度的影响,并在两种模型下比较了两级和传统的单级电荷按比例缩放DAC的精确度和版图面积.

Coupled high-resolution charge scaling DAC had small area and low power consumption. However, the parasitic capacitances on the interconnecting nodes of charge scaling DAC restricted the linearity of the DAC. A method to design the value of coupling capacitor in coupled high-resolution charge-scaling DAC is presented. It also discusses the impact of parasitic capacitance on DAC. Two different models are used to analyzing the impact of capacitor tracking error on DAC＇s accuracy. The potential accuracy and area of the two-stage charge scaling DAC and the conventional single-stage approach are compared in these models.