嵌入式CPU指令Cache的设计与实现

The Design-implementation of Embedded CPU Instruction Cache

针对嵌入式CPU指令处理速度与存储器指令存取速度不匹配问题,本文基于FPGA设计并实现了可以有效解决这一问题的指令Cache。根据嵌入式五级流水线CPU特性,所设计指令Cache的地址映射方式采用需要资源较少的直接映射(Direct Mapping),替换算法采用速度较快的先进先出(FIFO);使用VHDL实现指令Cache;对所设计指令Cache进行功能仿真和时序仿真并给出功能仿真结果。仿真结果表明了所设计指令Cache的有效性。

Aim at the mismatch between the speed of CPU working and the speed of accessing memory, a based on FPGA instruction cache was designed and implemented, and the instruction cache can resolve the mismatch. According to the property of embedded five stages pipeline CPU, the type of address mapping which is adopted in the instruction cache is direct mapping which needs lesser resource. FIFO algorithm is adopted in the instruction cache because the algorithm is fast in many algorithms. The cache was implemented with VHDL. The function simulation and time simulation were carried on the cache, and the result of the simulation was presented. The result shows that the instruction cache is effective.